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| 0 R Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information 0 DS077-1 (v2.1) July 9, 2003 0 Product Specification * System level features - SelectRAM+TM hierarchical memory: * 16 bits/LUT distributed RAM * Configurable 4K-bit true dual-port block RAM * Fast interfaces to external RAM - Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant - Low-power segmented routing architecture - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control * Eliminate clock distribution delay * Multiply, divide, or phase shift - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 19 high-performance interface standards * LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL * LVDS and LVPECL differential I/O - Up to 205 differential I/O pairs that can be input, output, or bidirectional - Hot swap I/O (CompactPCI friendly) Fully supported by powerful Xilinx ISE development system - Fully automatic mapping, placement, and routing - Integrated with design entry and verification tools - Extensive IP library including DSP functions and soft processors Maximum Available User I/O(1) 182 202 265 289 329 410 514 Maximum Differential I/O Pairs 83 86 114 120 120 172 205 Introduction The SpartanTM-IIE 1.8V Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The seven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz. Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven VirtexTM-E platform. Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-IIE family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs). * Features * Second generation ASIC replacement technology - Densities as high as 15,552 logic cells with up to 600,000 system gates - Streamlined features based on Virtex-E architecture - Unlimited in-system reprogrammability - Very low cost * Table 1: Spartan-IIE FPGA Family Members Logic Cells 1,728 2,700 3,888 5,292 6,912 10,800 15,552 Typical System Gate Range (Logic and RAM) 23,000 - 50,000 37,000 - 100,000 52,000 - 150,000 71,000 - 200,000 93,000 - 300,000 145,000 - 400,000 210,000 - 600,000 CLB Array (R x C) 16 x 24 20 x 30 24 x 36 28 x 42 32 x 48 40 x 60 48 x 72 Total CLBs 384 600 864 1,176 1,536 2,400 3,456 Distributed RAM Bits 24,576 38,400 55,296 75,264 98,304 153,600 221,184 Block RAM Bits 32K 40K 48K 56K 64K 160K 288K Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Notes: 1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 3 (c) 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS077-1 (v2.1) July 9, 2003 Product Specification www.xilinx.com 1-800-255-7778 1 Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information R General Overview The Spartan-IIE family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four columns and the XC2S600E has six columns of block RAM. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1). Spartan-IIE FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Xilinx offers multiple types of low-cost configuration solutions including the Platform Flash in-system programmable configuration PROMs. Spartan-IIE FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-IIE FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-IIE FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-IIE devices provide system clock rates beyond 200 MHz. Spartan-IIE FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-IIE FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features. Spartan-IIE Family Compared to Spartan-II Family * * * * * Higher density and more I/O Higher performance Unique pinouts in cost-effective packages Differential signaling - LVDS, Bus LVDS, LVPECL VCCINT = 1.8V - Lower power - 5V tolerance with external resistor - 3V tolerance directly PCI, LVTTL, and LVCMOS2 input buffers powered by VCCO instead of VCCINT Unique larger bitstream * * DLL DLL BLOCK RAM CLBs CLBs BLOCK RAM CLBs CLBs DLL I/O LOGIC DS077_01_052102 Figure 1: Basic Spartan-IIE Family FPGA Block Diagram 2 www.xilinx.com 1-800-255-7778 DS077-1 (v2.1) July 9, 2003 Product Specification BLOCK RAM DLL BLOCK RAM R Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information Spartan-IIE Product Availability Table 2 shows the package and speed grades available for Spartan-IIE family devices. Table 3 shows the maximum user I/Os available on the device and the number of user I/Os available for each device/package combination. Table 2: Spartan-IIE Package and Speed Grade Availability Pins Type Device XC2S50E Code -6 -7 XC2S100E -6 -7 XC2S150E -6 -7 XC2S200E -6 -7 XC2S300E -6 -7 XC2S400E -6 -7 XC2S600E -6 -7 144 Plastic TQFP TQ144 C, I C C, I C 208 Plastic PQFP PQ208 C, I C C, I C C, I C C, I C C, I C 256 Fine Pitch BGA FT256 C, I C C, I C C, I C C, I C C, I C C, I C 456 Fine Pitch BGA FG456 C, I C C, I C C, I C C, I C C, I C C, I C 676 Fine Pitch BGA FG676 C, I C C, I C Notes: 1. C = Commercial, TJ = 0 to +85 C; I = Industrial, TJ = -40 C to +100 C. Table 3: Spartan-IIE User I/O Chart Maximum User I/O 182 202 265 289 329 410 514 Available User I/O According to Package Type TQ144 102 102 PQ208 146 146 146 146 146 FT256 182 182 182 182 182 182 FG456 202 265 289 329 329 329 FG676 410 514 Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Notes: 1. User I/O counts include the four global clock/user input pins. DS077-1 (v2.1) July 9, 2003 Product Specification www.xilinx.com 1-800-255-7778 3 Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information R Ordering Information Example: Device Type Speed Grade XC2S50E -6 PQ 208 C Temperature Range Number of Pins Package Type Device Ordering Options Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Speed Grade -6 Standard Performance -7 Higher Performance Package Type / Number of Pins TQ144 144-pin Plastic Thin QFP Temperature Range (TJ ) C = Commercial I = Industrial 0C to +85C -40C to +100C PQ208 208-pin Plastic QFP FT256 FG456 FG676 256-ball Fine Pitch BGA 456-ball Fine Pitch BGA 676-ball Fine Pitch BGA Device Part Marking R Device Type Package Speed Operating Range SPARTAN XC2S50E PQ208xxx 6C R This line not related to device part number Sample package with part marking for XC2S50E-6PQ208C. ds077-1_02_070803 The Spartan-IIE Family Data Sheet DS077-1, Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information (Module 1) DS077-2, Spartan-IIE 1.8V FPGA Family: Functional Description (Module 2) DS077-3, Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics (Module 3) DS077-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables (Module 4) Revision History Date 06/27/02 11/18/02 07/09/03 Version No. 1.1 2.0 2.1 Updated -7 availability. Added XC2S400E and XC2S600E. Corrected XC2S150E max I/O count and XC2S50E differential I/O count and updated availability. Noted hot-swap capability. Updated Table 2 to show that all products are available. Clarified device part marking. www.xilinx.com 1-800-255-7778 DS077-1 (v2.1) July 9, 2003 Product Specification Description 4 |
Price & Availability of XC2S300E-6PQ208C
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